Nanoscale Thermal Transport in Vertical Gateall-around Junction-less Nanowire Transistors-Part II: Multiphysics Simulation

H. Rezgui (1, 2) , Mukherjee Chhandak (3, 2, 1) , Y. Wang (1, 2) , M. Deng (2, 1) , A. Kumar (4) , J. Müller (4) , G. Larrieu (4) , C. Maneux (2, 1)

1 UB - Université de Bordeaux
2 IMS - Laboratoire de l'intégration, du matériau au système
3 CNRS - Centre National de la Recherche Scientifique
4 LAAS-MPN - Équipe Matériaux et Procédés pour la Nanoélectronique

Today, extensive research has focused on heat propagation in emerging nanoelectronic devices. With advances in fabrication of nanowire transistors, thermal management has become a critical issue in cooling strategies and conducting materials. In this paper, we present a novel multiphysics analysis of the nanoscale thermal transport in 18 nm vertical junctionless gate-allaround silicon nanowire transistors. Based on this multiphysics analysis, we developed a new computational model derived from the Guyer-Krumhansl equation for describing heat transport within the nanoscale device. Our simulations results agree well with available theoretical approaches as well as measurement data.

Mots clés: Junctionless nanowire transistors; nanoscale thermal transport; Guyer-Krumhansl equation (GKE); thermal resistance; heat dissipation

Domaines: Sciences de l'ingénieur [physics]; Technologies Émergeantes [cs.ET]; Micro et nanotechnologies/Microélectronique; Electronique

H. Rezgui, Mukherjee Chhandak, Y. Wang, M. Deng, A. Kumar, et al.. Nanoscale Thermal Transport in Vertical Gateall-around Junction-less Nanowire Transistors-Part II: Multiphysics Simulation. IEEE Transactions on Electron Devices, 2023, 70 (12), pp.6505 - 6511. ⟨10.1109/TED.2023.3321280⟩. ⟨hal-04296531⟩